1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device including a plurality of semiconductor element devices having different junction depth of the diffusion layers and a method of fabricating the same.
2. Description of the Related Art
A technique that reduces the parasitic resistance of a source/drain diffusion layer by forming a silicide layer, e.g., a cobalt silicide layer, in the diffusion layer has been used to increase the operating speed and reduce the power consumption of a semiconductor device.
The problem that micropatterning of a semiconductor device makes the sheet resistance of a silicide layer nonuniform between an area where spacing between adjacent gate electrodes is 0.5 μm or less and an area where the gate electrode spacing is wider than that is pointed out (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-269482). This is so because when the gate electrode spacing decreases, the film thickness of a siliciding metal deposited on the surface decreases, and this decreases the thickness of a silicide layer to be formed. The technique disclosed in the above patent forms a very thin oxide film (about 0.7 nm thick) on the surface of a diffusion layer in which a silicide layer is to be formed, and deposits a siliciding metal while heating the substrate (to about 200° C.). This technique thus suppresses the silicidation reaction in an area where the gate electrode spacing is wide, thereby forming a silicide layer having a uniform sheet resistance regardless of the gate electrode spacing over the entire semiconductor wafer surface.